Interface ICs

Product Discontinuance Notice (PDN) for Integrated Device Technology, Inc. products.

Product Discontinuance Notice (PDN) for various IDT products, listing discontinued part numbers and replacements.

Product Discontinuance Notice (PDN) for certain Integrated Device Technology, Inc. (IDT) products.

The V386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second. This chip is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces through very low-swing LVDS signals.

The V386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second.

Product Discontinuance Notice (PDN) for certain IDT products, listing affected part numbers and replacements.

The V385A transmitter converts 28 bits of 3.3 V CMOS/TTL into 4 Low Voltage Differential Signaling (LVDS) data streams while the transmit clock input is transmitted in parallel with the data streams over a fifth LVDS link.

The V385A transmitter converts 28 bits of 3.3 V CMOS/TTL into 4 Low Voltage Differential Signaling (LVDS) data streams while the transmit clock input is transmitted in parallel with the data streams over a fifth LVDS link.

The V385A transmitter converts 28 bits of 3.3 V CMOS/TTL into 4 Low Voltage Differential Signaling (LVDS) data streams while the transmit clock input is transmitted in parallel with the data streams over a fifth LVDS link.

The V385A transmitter converts 28 bits of 3.3 V CMOS/TTL into 4 Low Voltage Differential Signaling (LVDS) data streams while the transmit clock input is transmitted in parallel with the data streams over a fifth LVDS link. Compared to the V385, the V385A provides an extended clock frequency range of 12-90 MHz, rather than 20-85 MHz.

The V103 LVDS display interface transmitter is primarily designed to support pixel data transmission between a video processing engine and a digital video display. The data rate supports up to SXGA+ resolutions.

The Tsi721 is IDT's solution for hardware-based PCIe Gen2 to RapidIO Gen2 protocol conversion in a bridging device.

The Tsi578 is a third generation RapidIO switch supporting 80 Gbits/s aggregate bandwidth. Tsi578 enhances system scalability and performance through support for mixed port configurations and extensive fabric management features.

The Tsi578 is a third-generation Serial RapidIO switch with 80 Gbits/s aggregate bandwidth, enhancing system scalability and performance.

The Tsi578 is a third generation RapidIO switch supporting 80 Gbits/s aggregate bandwidth. The Tsi578 is part of a family of switches that enable customers to develop systems with robust features and high performance at low cost.

The Tsi578 is a third generation RapidIO switch supporting 80 Gbits/s aggregate bandwidth.

The Tsi576 is part of IDT's third generation RapidIO switch family supporting 40 Gbps aggregate bandwidth.

The Tsi574TM is a third generation RapidIO switch supporting 40 Gbits/s aggregate bandwidth.

IDT Tsi572 Serial RapidIO Switch

The IDT Tsi568A is an industry leading Serial RapidIO switch supporting 80 Gbps aggregate bandwidth.

The Tsi568A Serial RapidIO Switch Hardware Manual discusses the features, capabilities, and configuration requirements for the Tsi568A.

The IDT Tsi568A is an industry leading Serial RapidIO switch supporting 80 Gbps aggregate bandwidth.

The IDT Tsi382 is a high-performance bus bridge that connects the PCI Express protocol to the PCI bus standard.

IDT's STAC9752/9753 are general purpose 20-bit, full duplex, audio CODECs conforming to the analog component specification of AC'97 (Audio CODEC 97 Component Specification Rev. 2.3).

IDT's STAC9752/9753 are general purpose 20-bit, full duplex, audio CODECs conforming to the analog component specification of AC'97 (Audio CODEC 97 Component Specification Rev. 2.3).

Value-Line Stereo AC'97 CODECs with headphone drive. General purpose, full duplex, audio CODECs conforming to AC'97 Rev. 2.2 with 18-bit ADCs and 20-bit DACs.

2-channel high definition audio CODEC compatible with Intel HD Audio interface.

The STAC9200 is a high quality, 2-channel audio CODEC compatible with the Intel High Definition (HD) Audio Interface. The STAC9200 provides Stereo 24-Bit resolution with sample rates up to 192KHz.

The STAC9200 is a high quality, 2-channel audio CODEC compatible with the Intel High Definition (HD) Audio Interface.

The STAC9200 is a high quality, 2-channel audio CODEC compatible with the Intel High Definition (HD) Audio Interface. It provides Stereo 24-Bit resolution with sample rates up to 192KHz.

2-channel high definition audio CODEC compatible with Intel HD Audio, providing 24-bit resolution up to 192KHz.

2-channel high definition audio CODEC compatible with Intel HD Audio Interface.

The NW6005 device is a single-chip, 3/5 Volt CMOS caller ID with call waiting detection circuit.

The NW6005 device is a single-chip, 3/5 Volt CMOS caller ID with call waiting detection circuit. It can receive signals following Bellcore GR-30-CORE & SR-TSV-002476, BT SIN227 & SIN242, and ETSI ETS 300 788-1/-2 specifications.

The MK712 Touch Screen Controller IC provides all the screen drive, A to D converter and control circuits to easily interface to 4-wire analog resistive touch screens.

The MK712 Touch Screen Controller IC provides all the screen drive, A to D converter and control circuits to easily interface to 4-wire analog resistive touch screens.

The MK712 Touch Screen Controller IC provides all the screen drive, A to D converter and control circuits to easily interface to 4-wire analog resistive touch screens.

This Product/Process Change Notice (PCN) from Integrated Device Technology, Inc. announces the addition of alternate Copper wire bond assembly facilities for TQFP-32 and TQFP-52 packages.

MC68EN302 Integrated Multiprotocol Processor with Ethernet

Enhanced Ethernet Transceiver supporting IEEE 802.3 AUI and 10BASE-T Twisted Pair interfaces, encoding NRZ to Manchester data.

The MC68150 Dynamic Bus Sizer is designed to allow the 32-bit MC68/LC/EC040 bus, or other 16- to 32-bit processors, to communicate bi-directionally with 32-, 16-, or 8-bit peripherals and memories.

3.3 V ECL/PECL quad differential receiver.

The MC100ES6017 is a 3.3 V ECL/PECL quad differential receiver.

Explanation of IDT part number suffixes for environmental, packaging, temperature, and package attributes.

A3G4250D and A3G4250DTR are 3-axis digital output gyroscope sensors

289 Pin Receivers

The VP386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.8 Gbps throughput or 350 Mbytes per second.

The VP386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.8 Gbps throughput or 350 Mbytes per second.

The V105A LVDS display interface transmitter is designed to support pixel data transmission between a video processing engine and a digital video display. The dual channel LVDS output supports pixel rates up to 150 MHz, enabling compatibility with 1080p and WUXGA display resolutions.

The 92HD71B7 codec is a low power optimized, high fidelity, 4-channel audio codec compatible with Intel's High Definition (HD) Audio Interface.