5M40ZE64I5N [Altera]

MAX V devices are low-cost, low-power, non-volatile CPLDs with instant-on (0.5ms or less) configuration time and standby current as low as 25µA. They feature fast propagation delay and clock-to-output times, an internal oscillator, and support for emulated RSDS (up to 200Mbps) and LVDS (up to 304Mbps) outputs. The devices include four global clocks, a user flash memory block of 8Kbits, and a single 1.8V external supply for the core. They support MultiVolt I/O interface (1.2V, 1.5V, 1.8V, 2.5V, 3.3V) and offer bus-friendly architecture with programmable slew rate, drive strength, bus-hold, and pull-up resistors. Schmitt triggers enable noise-tolerant inputs. The architecture is two-dimensional row- and column-based with logic array blocks (LABs) containing 10 logic elements (LEs) each, and MultiTrack interconnect for fast routing. I/O elements (IOEs) provide bidirectional I/O buffers. The devices are compliant with PCI-SIG PCI Local Bus Specification 2.2 for 3.3V operation, hot-socket compliant, and feature built-in JTAG BST circuitry (IEEE 1149.1-1990).