EP1C20F324C8N [Altera]

Cyclone devices are cost-effective FPGAs based on 1.5-V, 0.13-μm, all-layer copper SRAM process. They offer densities from 2,910 to 20,060 LEs and up to 294,912 RAM bits. Features include phase-locked loops (PLLs) for clocking, dedicated DDR interface support, and various I/O standards including LVDS at up to 640 Mbps and PCI. Devices support configuration through low-cost serial configuration devices and offer up to two PLLs per device with clock multiplication and phase shifting. The architecture consists of LABs with 10 LEs each, M4K RAM blocks (4K bits plus parity), and I/O elements at the periphery. Global clock network provides up to eight global clock lines.