EP20K400EFC672-3 [Altera]

The APEX 20K Programmable Logic Device Family features MultiCore architecture integrating LUT logic for register-intensive functions, product-term logic for combinatorial-intensive functions, and embedded system blocks (ESB) for memory functions including FIFO, dual-port RAM, and CAM. It offers high density with up to 1.5 million gates, 51,840 logic elements, 442,368 RAM bits, and 3,456 macrocells. The family supports low-power operation with 1.8V/2.5V supply voltages and MultiVolt I/O interface for 1.8V to 5.0V devices. Flexible clock management includes up to four PLLs with ClockLock, ClockBoost, and ClockShift features. I/O capabilities include LVDS up to 840 Mbits per channel, PCI compliance, and support for DDR SDRAM. Advanced interconnect uses FastTrack structure with dedicated carry/cascade chains. Packaging options range from 144 to 1,020 pins in TQFP, PQFP, RQFP, BGA, FineLine BGA, and PGA packages.