EP2AGX125EF29C6G [Altera]

The Arria II device family is a cost-optimized, 40-nm FPGA family featuring a low-power programmable logic engine and streamlined transceivers and I/Os. It includes Adaptive Logic Modules (ALM) for high logic efficiency, memory logic array blocks (MLABs) for small FIFOs, and high-performance DSP blocks up to 550MHz. The transceivers support up to 24 full-duplex channels with rates from 600Mbps to 6.375Gbps, and dedicated circuitry for protocols like PCIe Gen1/Gen2, Ethernet, and DDR3. It offers up to 726 user I/O pins in up to 20 banks, supporting various I/O standards including LVDS up to 1.25Gbps. Low power is achieved through architectural techniques and power optimizations in the Quartus II software. Security features include 256-bit AES encryption. The family is supported by development kits and a broad IP portfolio.