EP2AGX125EF35C6G [Altera]

The Arria II device family is a cost-optimized, 40-nm FPGA family featuring a low-power programmable logic engine and streamlined transceivers and I/Os. It supports common interfaces like PCIe, Ethernet, and DDR3 memory through Quartus II software, SOPC Builder, and Altera's IP solutions. Key features include Adaptive Logic Modules (ALM) with eight-input fracturable LUTs, MLABs for efficient small FIFOs, high-performance DSP blocks up to 550MHz with configurable multipliers (9x9 to 36x36), and hardened arithmetic functions. The devices integrate up to 24 full-duplex transceivers (600Mbps to 6.375Gbps) with dedicated circuitry for protocols including PCIe Gen1/Gen2, GbE, SRIO, CPRI, OBSAI, SDI, XAUI, SATA, and more. They offer up to 726 user I/O pins across 20 banks supporting various I/O standards, high-speed LVDS with SERDES/DPA (150Mbps-1.25Gbps), and advanced features like 256-bit AES encryption, on-chip termination, and parallel/serial configuration options.