EP3C40U484I7 [Altera]

The Cyclone III device family includes two variants: Cyclone III (lowest power, high functionality, lowest cost) and Cyclone III LS (lowest power FPGAs with security). Densities range from 5,000 to 200,000 logic elements (LEs) and 0.5 Mb to 8 Mb of memory, with static power consumption under 0.25 W. Cyclone III LS devices implement security features at silicon, software, and IP levels to protect against tampering, reverse engineering, and cloning, and support design separation for redundancy. Features include high memory-to-logic ratio, high I/O count, adjustable I/O slew rates, four PLLs per device, remote system upgrade, dedicated CRC checker for SEU, Nios II embedded processor support, pre-built IP cores, and support for high-speed external memory interfaces (DDR, DDR2, SDRSDRAM, QDRIISRAM) with auto-calibrating PHY. Vertical migration allows device optimization within the same package.