EP3SL110F780I4G [Altera]

The Stratix III FPGA family is designed for ease of use and rapid system integration, offering two variants: StratixIII L for balanced logic, memory, and multipliers for mainstream applications, and StratixIII E for memory- and multiplier-rich data-centric applications. It features Programmable Power Technology for low power consumption, selectable core voltage, up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks, up to 12 PLLs, memory interface support for DDR/DDR2/DDR3/RLDRAMII/QDRII/QDRII+ SRAM, up to 1,104 user I/O pins, dynamic on-chip termination, high-speed differential I/O with SERDES and DPA, support for high-speed networking standards, 256-bit AES security, hot socketing support, CRC for configuration memory error detection, ECC for memory blocks, Nios II processor support, and IP megafunction support. Based on a 1.1-V, 65-nm process, it is a programmable alternative to custom ASICs and processors for high-performance logic, DSP, and embedded designs.