EP910ILC-15 [Altera]

The Altera Classic EPLD family is a high-speed, low-power programmable logic device family with logic densities ranging from 300 to 900 usable gates. It features fast pin-to-pin logic delays as low as 10 ns and counter frequencies up to 100 MHz. Devices are available in various packages including DIP, PLCC, PGA, and SOIC. They include programmable security bits for design protection, are 100% generically tested, and support programmable registers for D, T, JK, and SR flipflops. Design is supported by Altera's MAX+PLUS II development system and third-party EDA tools.