EPM7032QC44-6 [INTEL]

The MAX 7000 family is a high-density, high-performance PLD family based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS EEPROM technology, it provides 600 to 5,000 usable gates, in-system programmability (ISP) via JTAG (in MAX7000S), pin-to-pin delays as fast as 5 ns, and counter frequencies up to 175.4 MHz. The devices feature a programmable power-saving mode, security bit, and MultiVolt I/O interface for 3.3V or 5.0V operation. They are available in a wide range of packages including PLCC, PGA, PQFP, RQFP, and TQFP.