EPM7064AETC44-10 [Altera]

High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX) architecture. Supports in-system programmability (ISP) through JTAG interface, pin-compatible with 5.0-V MAX7000S devices, ranging from 600 to 10,000 usable gates, with pin-to-pin delays as fast as 4.5 ns and counter frequencies up to 227.3 MHz. Available in various packages including PLCC, BGA, FineLine BGA, PQFP, and TQFP. Features include MultiVolt I/O interface, hot-socketing support, programmable interconnect array, PCI compatibility, programmable slew-rate control, and programmable power-saving mode.