EPM7512AEBC256-12 [INTEL]

High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX) architecture. Features include 3.3-V in-system programmability (ISP) through JTAG interface, built-in boundary-scan test (BST) circuitry, pin-compatible with 5.0-V MAX7000S devices, usable gates from 600 to 10,000, extended temperature range, MultiVolt I/O interface (5.0-V, 3.3-V, and 2.5-V logic levels), various package options (TQFP, PQFP, BGA, PLCC, FineLine BGA), hot-socketing support, programmable interconnect array (PIA) for fast performance, PCI-compatible, programmable power-saving mode, and programmable security bit.