EPM7512AEBI256-7 [INTEL]

MAX7000A devices are high-density, high-performance PLDs based on Altera's second-generation MAX architecture. They are EEPROM-based, operate with a 3.3-V supply voltage, and provide 600 to 10,000 usable gates, in-system programmability (ISP) via JTAG, pin-to-pin delays as fast as 4.5 ns, and counter speeds up to 227.3 MHz. The devices feature MultiVolt I/O interface (core at 3.3 V, I/O compatible with 5.0 V, 3.3 V, and 2.5 V), support hot-socketing (MAX 7000AE), and are available in a wide range of packages including PLCC, TQFP, PQFP, BGA, FineLine BGA, and Ultra FineLine BGA. Key features include programmable speed/power optimization, PCI compatibility, programmable slew-rate control, open-drain output, programmable macrocell registers, programmable power-up states (MAX 7000AE), programmable power-saving mode (50% power reduction per macrocell), configurable expander product terms (up to 32 per macrocell), programmable security bit, 6 to 10 output enable signals, two global clocks, enhanced interconnect resources, fast input setup times, and programmable ground pins. The devices are supported by Altera development systems (MAX+PLUS II and Quartus).