DIVIDE-E3-U [LATTICE]

The Divider IP core is a one-clock divider that completes one integer division per clock cycle. It supports signed or unsigned numerator and denominator with configurable data widths (4-64 bits), configurable output latency (1-64 cycles), and optional forced positive remainder. The core features optional clock enable and data valid ports, uses a non-restoring division algorithm, and is designed for Lattice FPGA families including LatticeECP3, LatticeECP2M, LatticeECP2, and LatticeXP2.