DSPIC33CH256MP206-E/PTVAO [Microchip]

Microchip’s dsPIC33CH family of digital signal controllers (DSCs) feature dual 90 & 100 MIPS 16-bit dsPIC® DSC cores with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors. These DSCs enable the design of switched mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC and other power circuits to reach the highest possible energy efficiency.  These devices are also ideal for many advanced sensing and control, touch, high-performance general-purpose and robust applications.

These dual-core DSCs are a good fit for complex yet cost-effective advanced sensing, core-independent touch, motor, and digital power applications.

The dsPIC33CH product family has many hardware features that help simplify functional safety certifications for ASIL-B/-C and SIL-2/-3 focused automotive and industrial safety-critical applications. The family offers ISO 26262 and IEC 61508 Functional Safety packages containing FMEDA report, safety manual, diagnostic libraries and more. 

• Learn more about Functional Safety capabilities including hardware, software, and supporting collateral

Operating Conditions
• 3V to 3.6V, -40°C to +150°C

Core: Dual Core dsPIC33CH DSCs
• Main Core 90 MHz and Secondary Core 100 MHz Operation
• Independent Peripherals for Main Core and Secondary Core
• Configurable Shared Resources for Main Core and Secondary Core
• Fast 6-Cycle Divide
• Message Boxes and FIFO to Communicate Between Main and Secondary (MSI)
• Code Efficient (C and Assembly) Architecture
• 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle, Mixed-Sign MUL Plus 6-Cycle Hardware Divide
• 32-Bit Multiply Support
• Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response
• Zero Overhead Looping

High Performance Peripherals for Real Time Control
• 4 x 12-bit 3.5 MSPS ADCs: 34 Channels
• High Speed PWMs with 250ps resolution, 12x2 Channels
• Optimized for high-performance digital power, motor control and applications requiring sophisticated algorithms

Main Core features
• Core Frequency: 90 MHz
• Program Flash: 512/256 Kbytes Dual Partition with LiveUpdate
• Data RAM: 48/32 Kbytes
• 16-Bit Timer: 1
• DMA: 6
• SCCP (Capture/Compare/Timer): 8
• UART: 2
• SPI/I2S: 2
• I2C: 2
• CAN Flexible Data-Rate (FD): 2 ('50x devices only)
• SENT: 2
• CRC: 1
• QEI: 1
• PTG:1
• CLC: 4
• 16-Bit High-Speed (250ps) PWM: 4x2
• 12-bit, 3.5 Msps ADC: 1, 16 Channels
• Digital Comparator: 4
• 12-Bit DAC/Analog CMP Module: 1
• Watchdog Timer: 1
• Deadman Timer: 1
• Breakpoints: 3 complex, 5 simple
• Oscillator: 1

Secondary Core features
• Core Frequency: 100 MHz
• Program Memory: 72 Kbytes (PRAM) Dual Partition with LiveUpdate
• Data RAM: 16 Kbytes
• 16-Bit Timer: 1
• DMA: 2
• SCCP (Capture/Compare/Timer): 4
• UART: 1
• SPI/I2S: 1
• I2C: 1
• QEI: 1
• CLC: 4
• 16-Bit High-Speed (250ps) PWM: 8x2 Channels
• 12-bit, 3.5 Msps ADC: 3, 18 Channels
• Digital Comparator: 4
• 12-Bit DAC/Analog CMP Module: 3
• Watchdog Timer: 1
• Deadman Timer: 1
• Breakpoints: 1 complex, 2 simple
• Oscillator: 1

Clock Management
• Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Main Reference Clock Output
• Secondary Reference Clock Output
• Fail-Safe Clock Monitor (FSCM)
• Fast Wake-up and Start-up
• Backup Internal Oscillator
• LPRC Oscillator

Power Management
• Low-Power Management Modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset

Debugger Development Support
• In-Circuit and In-Application Programming
• Simultaneous Debugging Support for Main and Secondary Cores
• Main Only Debug and Secondary Only Debug Support
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace Buffer and Run-Time Watch

Core Independent Touch
• Uses Peripheral Trigger Generator (PTG) and High-speed ADCs
• Ready-to-use touch library support in MPLAB Code Configurator (MCC)

Functional Safety Support (ISO 26262 and IEC 61508)
• ISO 26262 and IEC 61508 Functional Safety Ready
• ASIL B automotive safety applications – ISO 26262
• SIL 2 industrial safety applications – IEC 61508
• ISO 26262 and IEC 61508 Functional Safety Packages

Embedded Security
• CodeGuard security together with Flash OTP by ICSP Write Inhibit enables implementing Immutable Secure Boot
• Flash OTP by ICSP Write Inhibit to configure entire Flash as OTP
• Option to disable entry to the debug mode
• User OTP
• Enables implementing robust security use cases together with CryptoAuthentication and CryptoAutomotive devices such as:
• Secure Boot
• Secure Firmware Upgrade
• Secure Communication
• Node Authentication and more

Functional Safety hardware features
• Dead-Man Timer (DMT) safety feature clocked by instruction fetches
• Watch Dog Timer (WDT)
• CodeGuard™ security for program FLASH
• Programmable Cyclic Redundancy Check (CRC)
• FLASH ECC Fault Injection testing feature
• Flash OTP by ICSP™ write inhibit
• Class B Safety Library, IEC 60730
• RAM Memory Built-In Self Test (MBIST)
• Two-Speed Start-up
• Fail-Safe Clock Monitoring (FSCM)
• Backup FRC (BFRC)
• Capless Internal Voltage Regulator
• Virtual Pins for Redundancy and Monitoring
• Multiple redundant clock sources
• I/O Port read-back
• Analog peripherals redundancies
• Hardware traps
• SFR locks
• Write protection
• Shadow working registers

AUTOSAR-Ready DSC supporting
• AUTOSAR (4.3.x)
• ASIL B- and ASPICE-compliant MCAL drivers
• ISO 26262 Functional Safety and Automotive Security