DSPIC33CK1024MP410T-E/PT [Microchip]

Microchip’s dsPIC33CK family of digital signal controllers (DSCs) features a single 100 MHz dsPIC^® DSC core with integrated DSP and enhanced on-chip peripherals for advanced sensing and control, touch, robust general embedded, motor control, digital power and high-performance embedded applications. The DSCs feature advanced analog for advanced sensor interfacing designs. Offering real-time deterministic performance, the DSCs enable high-performance control applications.

Integrated with hardware peripherals that enable robust and complex touch-sensing designs, these core-independent touch DSCs can address additional design requirements involving AUTOSAR, functional safety, security, and CAN/CAN FD.

These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors.

This DSC family is also ideal for switched mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC and other power circuits to reach the highest possible energy efficiency.  These devices are also ideal for high-performance general-purpose and robust applications.

Developed following ISO 26262 process and IEC 61508 processes, the dsPIC33CK family is ISO 26262 and IEC 61508 compliant. The dsPIC33CK product family has many hardware features that help simplify functional safety certifications targeting up to ASIL-B and SIL-2 focused automotive and industrial safety-critical applications. The family offers ISO 26262 and IEC 61508 Functional Safety packages containing FMEDA report, safety manual, diagnostic libraries and more.

• Learn more about ISO 26262 and IEC 61508 Functional Safety capabilities including hardware, software, and supporting collateral

Operating Conditions
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 100 MHz
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 70 MHz

dsPIC33CK DSC Core
• Up to 1024 KBytes of Program Flash with ECC
• Up to 128 KBytes of Data SRAM with Memory Built in Self-Test (MBIST)
• Code efficient (C and Assembly) CPU architecture designed for real-time applications
• 5 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
• Single-cycle, mixed-sign 32-bit MUL
• Fast 6-cycle hardware 32/16 and 16/16 DIV
• Dual 40-bit fixed point Accumulators (ACC) for DSP operations
• Single-cycle MAC/MPY with dual data fetch and result write-back
• Zero overhead looping support

Core Independent Touch
• Uses Peripheral Trigger Generator (PTG) and High-speed ADCs
• Ready-to-use touch library support in MPLAB Code Configurator (MCC)

Functional Safety Support (ISO 26262 and IEC 61508)
• ISO 26262 and IEC 61508 compliant development
• Automotive safety applications targeting up to ASIL-B
• Industrial safety applications targeting up to SIL-2
• ISO 26262 and IEC 61508 Functional Safety Packages

Embedded Security
• CodeGuard security together with Flash OTP by ICSP Write Inhibit enables implementing Immutable Secure Boot
• Flash OTP by ICSP Write Inhibit to configure entire Flash as OTP
• User OTP
• Enables implementing robust security use cases together with CryptoAuthentication and CryptoAutomotive devices such as:
• Secure Boot
• Secure Firmware Upgrade
• Secure Communication
• Node Authentication and more

AUTOSAR-Ready DSC supporting
• AUTOSAR (4.3.x)
• ASIL B- and ASPICE-compliant MCAL drivers
• ISO 26262 Functional Safety and Automotive Security

High-Speed PWM Module
• Up to 12 independent PWM pairs (24 total outputs) with up to 250ps resolution
• Dead-time insertion for rising and falling edges and dead-time compensation support
• Clock chopping for high-frequency operation
• Fault and current limit inputs
• Flexible trigger configuration for ADC triggering

Advanced Analog Features
• 5x 12-bit 3.5 MSPS ADC Modules each with 4 dedicated SARs and 1 shared SAR cores (5 S&Hs)
• Up to 28 ADC input channels
• 5 digital comparators for reducing CPU overhead
• 5 oversampling filters for increased resolution
• Up to 6 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation
• Up to 3 op amps with internal connection to ADC Module

Timer/Counters/Output Compare/Input Capture
• 24x 16-bit timer/counters (up to 12x 32-bit)
• 14 PWM or Output Compare (OC) outputs
• 9 Input Captures (IC) pins or internal connections from the CLC or Comparator Modules
• 3 Quadrature Encoder Interface (QEI) modules for optical encoder support
• Peripheral Trigger Generator (PTG) for scheduling complex sequences

Communication Interfaces
• 3 UARTs (15 Mbps) with automated protocol handling for LIN2.2, DMX and IrDA®
• 3x 4-wire SPI/I2S, up to 40 MHz operation on SPI with dedicated pins
• 3 I2C Modules (up to 1 Mbps) with SMBus support
• 2 CAN Flexible Data Rate (CAN-FD) Module ("7xx devices only)
• 2 Single-Edge Nibble Transmission (SENT) Modules for sensor interfacing
• 8 DMA channels supporting UART, SPI, ADC, CAN-FD, IC, OC and Timer data transfers

Clock and Power Management
• On-chip 8 MHz Fast RC (FRC) and 32 kHz Low-Power RC (LPRC) oscillators
• Programmable PLLs with external oscillator clock sources and Reference Clock Output (REFO)
• Fail-Safe Clock Monitor (FSCM) with 8 MHz Back-up Fast RC (BFRC) oscillator
• Low-Power management modes - Sleep, Idle and Doze
• Integrated Power-on Reset (POR) and Brown-Out Reset (BOR)

Debugger Development Support
• In-Circuit and in application programming and debug support (ICSP)
• On-chip debug trace buffer and run-time watch with 3 complex and 5 simple breakpoints
• IEEE 1149.2 (JTAG) boundary scan support

Safety Features
• Dead-Man Timer (DMT) safety feature clocked by instruction fetches
• Watch Dog Timer (WDT)
• CodeGuard™ security for program Flash
• Programmable Cyclic Redundancy Check (CRC)
• Flash ECC Fault Injection testing feature
• Flash OTP by ICSP™ write inhibit
• RAM Memory Built-In Self Test (MBIST)
• Two-Speed Start-up
• Fail-Safe Clock Monitoring (FSCM)
• Backup FRC (BFRC)
• Virtual Pins for Redundancy and Monitoring
• Multiple redundant clock sources
• I/O Port read-back
• Analog peripherals redundancies
• Hardware traps
• SFR locks
• Write protection
• Shadow working registers