SY10E241JZ [Microchip]

The SY10/100E241 are 8-bit shiftable registers designed for use in new, high-performance ECL systems. The E241 features internal data feedback organized such that the SHIFT control overrides the HOLD, /LOAD control. This configuration also enables switching to scan mode with the single SHIFT control line. The eight inputs D0–D7 accept parallel input data, while S-IN accepts serial input data when in shift mode. Data is accepted a set-up time before the rising edge of CLK. Shifting is also accomplished on the rising clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.