74HCT138N,652 [NXP]

The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs and one inverter. The '138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Wide supply voltage range from 2.0 to 6.0 V, CMOS low power dissipation, high noise immunity, latch-up performance exceeds 100 mA per JESD 78 Class II Level B, demultiplexing capability, multiple input enable for easy expansion, ideal for memory chip select decoding, active LOW mutually exclusive outputs, input levels: CMOS level (74HC138) and TTL level (74HCT138), complies with JEDEC standards, ESD protection: HBM exceeds 2000 V, CDM exceeds 1000 V, multiple package options, specified from -40 °C to +85 °C and from -40 °C to +125 °C.