DSP56301PW80 Description

The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors

(DSPs). This family uses a high-performance, single-clock cycle per instruction engine. Significant architectural

features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The

DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.0?3.6 volts. The DSP56300 core family

offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling

wireless, telecommunications, and multimedia products.

DSP56301PW80 Features

80/100 million instructions per second (MIPS) with an 80/100 MHz clock at 3.0?3.6 V

Object code compatible with the DSP56000 core with the highly parallel instruction set

Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and output clock with skew elimination

Hardware debugging support including On-Chip Emulation (OnCE?) module, Joint Test Action Group (JTAG) Test Access Port (TAP)

Serial communications interface (SCI) with baud rate generator

Triple timer module

Up to forty-two programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled

DSP56301PW80 Applications

Wireless and wireline infrastructure applications

Multi-channel wireless local loop systems

DSP resource boards

High-speed modem banks

Packet telephony