STM32H503CBT7 [STMicroelectronics]

The STM32H503xx devices are a high-performance microcontrollers family (STM32H5 series) based on the high-performance Arm^® Cortex^®-M33 32-bit RISC core. They operate at a frequency of up to 250 MHz.

The Cortex^®-M33 core features a single-precision floating-point unit (FPU) that supports all the Arm^® single-precision data-processing instructions and all the data types.

The Cortex^®-M33 core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application security.

The devices embed high-speed memories (128 Kbytes of dual bank flash memory and 32 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to three APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix.

The devices feature several protection mechanisms for embedded flash memory and SRAM: secure life cycle management, write protection and hide protection areas.

The devices embed several peripherals reinforcing security: a HASH hardware accelerator and a true random number generator.

The devices offer active tamper detection and protection against transient and environmental perturbation attacks. It is done thanks to several internal monitoring that generate a secret data erase in case of an attack.

The devices offer a fast 12-bit ADC, two DAC channels, an OPAMP, a comparator, a low-power RTC, one 32-bit general-purpose timer, one 16-bit PWM timer dedicated to motor control, one 16-bit general-purpose timer, two 16-bit basic timers and two 16-bit low-power timers.

The devices also feature standard and advanced communication interfaces such as: two I²Cs, two I3Cs shared with I²C, three SPIs with muxed full-duplex I2S, three USARTs and one low-power UART, one FDCAN, and one USB full-speed.

The devices operate in the - 40 to + 85 °C/105 °C, and up to 125 °C at low dissipation (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.

A comprehensive set of power-saving modes allows the design of low-power applications.

Some independent power supplies are supported like an analog independent supply input for ADC, DACs, COMP and OPAMP, and a dedicated supply input for some GPIOs. A VBAT input is available for connecting a backup battery. This battery preserves the RTC functionality and backup 32x 32-bit registers and 2-Kbyte SRAM.

The devices offer five packages from 25-pin to 64-pin.

• Core
  • Arm^® Cortex^®-M33 CPU with FPU, frequency up to 250 MHz, MPU, 375 DMIPS (Dhrystone 2.1), and DSP instructions
    
• ART Accelerator
  • 8-Kbyte instruction cache allowing 0-wait-state execution from flash memory (frequency up to 250 MHz)
    
• Benchmarks
  • 1.5 DMIPS/MHz (Drystone 2.1)
    
  • 1023 CoreMark^® (4.092 CoreMark^®/MHz)
    
• Memories
  • 128 Kbytes of embedded flash memory with ECC, two banks of read-while-write
    
  • 2-Kbyte OTP (one-time programmable)
    
  • 32-Kbyte SRAM with ECC
    
  • 2 Kbytes of backup SRAM (available in the lowest power modes)
    
• Clock, reset, and supply management
  • 1.71 V to 3.6 V application supply and I/O
    
  • POR, PDR, PVD, and BOR
    
  • Embedded regulator (LDO)
    
  • Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
    
  • Two PLLs for system clock, USB, audio, and ADC
    
  • External oscillators: 4 to 50 MHz HSE, 32.768 kHz LSE
    
• Low-power modes
  • Sleep, Stop and Standby modes
    
  • V_BAT supply for RTC, 32 backup registers (32 bits)
    
• General-purpose inputs/outputs
  • Up to 49 fast I/Os with interrupt capability (most 5 V tolerant)
    
  • Up to 9 I/Os with independent supply down to 1.08 V
    
• Analog
  • One 12-bit ADC, up to 2.5 MSPS
    
  • One 12-bit dual-channel DAC
    
  • One ultra-low-power comparator
    
  • One operational amplifier (7 MHz bandwidth)
    
  • One digital temperature sensor
    
• Up to 11 timers
  • Six 16-bit (including two low-power 16-bit timer available in Stop mode) and one 32-bit timer
    
  • Two watchdogs
    
  • One SysTick timer
    
  • RTC with hardware calendar, alarms, and calibration
    
• Communication interfaces
  • Up to two I2Cs FM + interfaces (SMBus/PMBus^®)
    
  • Up to two I3Cs shared with I2C
    
  • Up to three USARTs (ISO7816 interface, LIN, IrDA, modem control) and one LPUART
    
  • Up to three SPIs including three muxed with full-duplex I2S for audio class accuracy via internal audio PLL or external clock and up to three additional SPI from three USART when configured in synchronous mode
    
  • One FDCAN
    
  • One USB 2.0 full-speed host and device
    
• Two DMA controllers to offload the CPU
• Security
  • HASH (SHA-1, SHA-2), HMAC
    
  • True random generator
    
  • 96-bit unique ID
    
  • Active tamper
    
• Debug
  • Authenticated debug
    
  • Serial wire-debug (SWD) and JTAG interfaces
    
• ECOPACK2 compliant packages