STM32H523CET7TR [STMicroelectronics]

The STM32H523xx devices are high-performance microcontrollers of the STM32H5 series, based on the high-performance Arm^® Cortex^®-M33 32-bit RISC core. They operate at a frequency of up to 250 MHz.

The Cortex^®-M33 core features a single-precision floating-point unit (FPU), which supports all the Arm^® single-precision data-processing instructions and all the data types. This core implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application security.

The devices embed high-speed memories (512 Kbytes of dual bank flash memory and 272 Kbytes of SRAM), a flexible external memory controller (FMC) for devices with packages of 100 pins and more, one OCTOSPI memory interface (at least one Quad-SPI available on all packages), and an extensive range of enhanced I/Os and peripherals connected to three APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix.

The devices offer security foundation compliant with the trusted-based security architecture (TBSA) requirements from Arm^®. Besides these capabilities, the devices incorporate a secure firmware installation that allows the customer to secure the provisioning of the code during its production. A flexible life cycle is managed thanks to multiple levels of protection and secure debug authentication. Firmware hardware isolation is supported thanks to securable peripherals, memories, and I/Os, and to privilege configuration of peripherals and memories.

The devices feature several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, secure, and hide protection areas.

Dedicated peripherals reinforce security: an HASH hardware accelerator, and a true random number generator.

The devices offer active tamper detection and protection against transient and environmental perturbation attacks, thanks to several internal monitoring, generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications.

The devices offer two fast 12-bit ADCs, two DAC channels, an internal voltage reference buffer, a low-power RTC, two 32-bit general-purpose timers, two 16-bit PWM timers dedicated to motor control, eight 16-bit general-purpose timers, two 16-bit basic timers, and six 16-bit low-power timers.

The devices also feature standard and advanced communication interfaces, namely: three I²Cs, two I3Cs, four SPIs with three muxed full-duplex I2S, four USARTs, two UARTs and one low-power UART, one SDMMC, two FDCANs, one USB full-speed, one USB Type-C^®/USB power delivery controller.

The devices operate in the -40 to +85 °C/105 °C (+130 °C junction), and to 125 °C at low dissipation temperature range, with a 1.71 to 3.6 V power supply.

A comprehensive set of power-saving modes allow the design of low-power applications.

Independent power supplies are supported: an analog independent supply input for ADC, DACs, a 3.3 V dedicated supply input for USB, and a dedicated supply input for some GPIOs and SDMMC. A VBAT input is available to connect a backup battery, to preserve the RTC functionality, and to backup 32 32-bit registers and a 2-Kbyte SRAM.

The devices offer eight packages, from 39 to 144 pins.

• Core
  • Arm^® Cortex^®-M33 CPU with TrustZone^®, FPU, frequency up to 250 MHz, MPU, 375 DMIPS (Dhrystone 2.1)
    
• ART Accelerator
  • 8-Kbyte instruction cache allowing 0-wait-state execution from flash and external memories
    
  • 4-Kbyte data cache for external memories
    
• Benchmarks
  • 1.5 DMIPS/MHz (Drystone 2.1)
    
  • 1023 CoreMark^® (4.092 CoreMark^®/MHz)
    
• Memories
  • Up to 512 Kbytes of embedded flash memory with ECC, two banks read-while-write
    
  • Up to 48-Kbyte per bank with high-cycling capability (100 K cycles) for data flash
    
  • 2-Kbyte OTP (one-time programmable)
    
  • 272 Kbytes of SRAM (80-Kbyte SRAM2 with ECC)
    
  • 2 Kbytes of backup SRAM available in the lowest power modes
    
  • Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, NOR/NAND memories
    
  • One Octo-SPI memory interface with support for serial PSRAM/NAND/NOR, hyper RAM/flash frame formats
    
  • One SD/SDIO/MMC interface
    
• Clock management
  • Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
    
  • External oscillators: 4-50 MHz HSE, 32.768 kHz LSE
    
• General-purpose inputs/outputs
  • Up to 112 fast I/Os with interrupt capability (most of them 5 V-tolerant)
    
  • Up to ten I/Os with independent supply down to 1.08 V
    
• Low-power consumption
  • Sleep, Stop, and Standby modes
    
  • V_BAT supply for RTC, 32 backup registers (32-bit)
    
• Security
  • Arm^® TrustZone^® with Armv8-M mainline security extension
    
  • Up to eight configurable SAU regions
    
  • TrustZone^® aware and securable peripherals
    
  • Flexible life cycle scheme with secure debug authentication
    
  • SESIP3 and PSA Level 3 certified assurance target
    
  • SFI (secure firmware installation)
    
  • Root of trust thanks to unique boot entry and secure hide protection area (HDP)
    
  • Secure firmware upgrade support with TF-M
    
  • Public key accelerator, ECDSA signature verification
    
  • HASH hardware accelerator
    
  • True random number generator, NIST SP800-90B compliant
    
  • 96-bit unique ID
    
  • Active tampers
    
• Two DMA controllers to offload the CPU
  • Two dual-port DMAs with FIFO
    
• Reset and supply management
  • 1.71 V to 3.6 V application supply and I/O
    
  • POR, PDR, PVD, and BOR
    
  • Embedded regulator with configurable scalable output to supply the digital circuitry
    
• Up to 16 timers
  • Ten 16-bit timers (including two low-power16-bit timers available in Stop mode)
    
  • Two 32-bit timers with up to four IC/OC/PWM or pulse counters and quadrature (incremental) encoder input
    
  • Two watchdogs
    
  • Two SysTick timers
    
• Up to 21 communication interfaces
  • Up to three I2Cs Fm+ (SMBus/PMBus^®)
    
  • Two I3Cs
    
  • Up to six U(S)ARTs (ISO7816 interface, LIN, IrDA, modem control) and one LPUART
    
  • Up to four SPIs, including three muxed in full-duplex I2S audio class accuracy via internal audio PLL or external clock, and up to four additional SPIs from four USARTs when configured in Synchronous mode (one additional SPI with OctoSPI)
    
  • Two FDCAN controllers
    
  • One 8- to 14-bit camera interface
    
  • One 16-bit parallel slave synchronous-interface
    
  • One HDMI-CEC
    
  • One USB 2.0 full-speed host and device (crystal-less)
    
  • One USB Type-C^®/USB Power Delivery r3.1
    
• Analog
  • Two 12-bit ADCs with up to 5 Msps in 12-bit
    
  • One 12-bit DAC with two channels
    
  • Digital temperature sensor
    
  • Voltage reference buffer
    
• Debug
  • Authenticated debug and flexible device life cycle
    
  • Serial wire-debug (SWD), JTAG, Embedded Trace Macrocell™ (ETM)
    
• ECOPACK2 compliant packages