STPMIC1LAPQR [STMicroelectronics]

The STPMIC1L is a fully integrated power management IC designed for STM32MP1x MPU series applications requiring low power and high efficiency.

The device integrates advanced low-power features controlled by a host processor via I²C and I/O interfaces.

The STPMIC1L regulators are designed to supply power to the application processor as well as to external system peripherals such as DDR, and flash memories. The STPMIC1L supplies the core chipset (the MPU+ DDR+ 1 flash memory), but not other system devices. This is done via discrete regulators controlled by the STPMIC1L GPOs).

Two buck SMPS are optimized to provide excellent transient response and output voltage precision for a wide range of operating conditions. Advanced PWM phase-shift synchronization technique with integrated PLL reduces noise and EMI.

• Input voltage range from 2.8 V to 5.5 V
• 2 buck SMPS converters with adaptive constant on-time (COT) topology
• 2 adjustable general-purpose LDOs
• 1 LDO for DDR3L/DDR4 termination (sink-source) or as a general-purpose LDO
• 1 LDO for USB PHY supply
• 2 MHz switching frequency buck converters with forced PWM
• User programmable non-volatile memory (NVM), enabling scalability to support a wide range of applications
• Immediate output alternate settings toggle via dedicated power control pins
• Programmable output voltages turn ON/OFF sequences
• I²C and digital I/O control interfaces
• 2 GPO output controls for external commands
• VFQFPN 28L (4.0 x 4.0 x 1.0 mm)