CDC857-2DGG [Texas Instruments]

The CDC857-2 and CDC857-3 are PLL clock drivers that use a PLL to precisely align the feedback output to the clock input signal in both frequency and phase. They provide ten low-skew, low-jitter copies of the CLK input through one bank of ten inverting and noninverting outputs. Output duty cycles are adjusted to 50% independent of the input duty cycle. The devices feature an on-chip loop filter, eliminating the need for external RC networks. The CDC857-3 operates at 3.3V for the PLL and 2.5V for the output buffer, while the CDC857-2 operates at 2.5V for both. All outputs can be enabled or disabled via a single output enable input (G). The devices require a stabilization time to achieve phase lock and are characterized for operation from 0°C to 85°C.