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    5. DRA725AGGABCQ1 Texas Instruments
    Product FAQ

    1. Is DRA725AGGABCQ1 available for RFQ?

    Yes. DRA725AGGABCQ1 by Texas Instruments is available for RFQ. Submit your required quantity and our team will confirm real-time stock, lead time, and volume pricing.

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    3. What are the key specifications of DRA725AGGABCQ1?

    DRA725AGGABCQ1 is a Texas Instruments Processors - Application Specialized with Operating temperature range (°C): -40 to 125 and Graphics acceleration: 1 2D, 1 3D. Review the product details or submit an RFQ if you need confirmation before purchase.

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    Part Number:

    DRA725AGGABCQ1

    Manufacturer:

    Texas Instruments

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    DRA725AGGABCQ1 [Texas Instruments]

    DRA725AGGABCQ1
    DRA725AGGABCQ1

    Part No:

    DRA725AGGABCQ1

    Category:

    Processors - Application Specialized

    Manufacturer:

    Texas Instruments

    Description:

    1.2 GHz Arm Cortex-A15 SoC processor with graphics and DSP for automotive infotainment & cluster

    RoHS Status:

    Datasheet:

    Stock Status:

    Available for RFQ

    Pricing:

    Request Volume Pricing

    Quote Response:

    Within 24 Hours

    Shipping:

    In-stock parts ship in 1–2 business days

    Specification

    Type
    Parameter
    Arm CPU
    1 Arm Cortex-A15
    Arm (max) (MHz)
    1176
    Coprocessors
    2 Dual Arm Cortex-M4
    CPU
    1 Arm Cortex-A15
    Graphics acceleration
    1 2D, 1 3D
    Display type
    1 HDMI, 3 LCD
    Protocols
    Ethernet
    Ethernet MAC
    1-Port 10/100/1000, 2-Port 1Gb switch
    PCIe
    2 PCIe Gen 2
    Hardware accelerators
    Audio tracking logic, Image video accelerator, Viterbi decoder
    Features
    Multimedia

    Products Detail

    DRA72x ("Jacinto™ 6 Eco") infotainment applications processors are developed on the same architecture as Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

    DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family, allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution.

    Programmability is provided by a single-core Arm® Cortex®-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm® processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

    Additionally, TI provides a complete set of development tools for the Arm®, and DSP, including C compilers and a debugging interface for visibility into source code execution.

    Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment is available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

    The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard.

    • Architecture designed for infotainment applications
    • Video, image, and graphics processing support
      • Full-HD video (1920 × 1080p, 60 fps)
      • Multiple video inputs and video outputs
      • 2D and 3D graphics
    • Arm® Cortex®-A15 microprocessor subsystem
    • C66x floating-point VLIW DSP cores
      • Fully object-code compatible with C67x and C64x+
      • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
    • Up to 512KB of on-chip L3 RAM
    • Level 3 (L3) and level 4 (L4) interconnects
    • DDR3/DDR3L External Memory Interface (EMIF) module
      • Supports up to DDR3-1333 (667 MHz)
      • Up to 2GB across single chip select
    • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
    • IVA-HD subsystem
    • Display subsystem
      • Display controller with DMA engine and up to three pipelines
      • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
    • 2D-graphics accelerator (BB2D) subsystem
      • Vivante® GC320 core
    • Video Processing Engine (VPE)
    • Single-core PowerVR™ SGX544 3D GPU
    • One Video Input Port (VIP) module
      • Support for up to four multiplexed input ports
    • General-Purpose Memory Controller (GPMC)
    • Enhanced Direct Memory Access (EDMA) controller
    • 2-Port Gigabit Ethernet switch
      • Up to two external ports
    • Sixteen 32-bit general-purpose timers
    • 32-bit MPU watchdog timer
    • Six high speed Inter-Integrated Circuit (I2C™) ports
    • HDQ/1-Wire® interface
    • Ten configurable UART/IrDA/CIR modules
    • Four Multichannel Serial Peripheral Interfaces (McSPI)
    • Quad Serial Peripheral Interface (QSPI)
    • Media Local Bus subsystem (MLBSS)
    • Real-Time Clock subsystem (RTCSS)
    • SATA interface
    • Eight Multichannel Audio Serial Port (McASP) modules
    • SuperSpeed USB 3.0 dual-role device
    • High Speed USB 2.0 dual-role device
    • High Speed USB 2.0 on-the-go
    • Four MultiMedia Card/Secure Digital®/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
    • PCI-Express® (PCIe®) revision 3.0 subsystems with two 5-Gbps lanes
      • One 2-lane Gen2-compliant port
      • or two 1-lane Gen2-compliant ports
    • Dual Controller Area Network (DCAN) modules
      • CAN 2.0B Protocol
    • MIPI® Camera Serial Interface 2 (CSI-2)
    • Up to 215 General-Purpose I/O (GPIO) pins
    • Device security features
      • Hardware crypto accelerators and DMA
      • Firewalls
      • JTAG lock
      • Secure keys
      • Secure ROM and Boot
      • Customer programmable keys (Silicon Revision 2.1)
    • Power, reset, and clock management
    • On-chip debug with CTools technology
    • 28-nm CMOS technology
    • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)

    Documents

    User guide:

    DRA71x and DRA72x Technical Reference Manual (Rev. D)
    Featured Product
    Operating system
    Android, Linux, RTOS
    Security
    Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection
    Rating
    Automotive
    Operating temperature range (°C)
    -40 to 125
    Package
    FCBGA (ABC)
    Pins
    760
    Size
    529 mm² 23 x 23
    REACH Status
    Yes
    RoHS Status
    RoHS Compliant
    DM369 Camera Starter Kit (CSK) User's Guide
    Jacinto6 Android Video Decoder Software Design Specification User's Guide

    EVM User's guide:

    DRA72x EVM CPU Board User's Guide

    Data sheet:

    DRA72x Infotainment Applications Processor Silicon Revision 2.0 and 2.1 datasheet (Rev. H)

    Errata:

    DRA72x and DRA71x SoC for Automotive Infortainment Silicon Errata (Rev. F)

    Application note:

    Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOCIVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoCAM57x, DRA7x, and TDA2x EMIF Tools (Rev. E)Integrating New Cameras With Video Input Port on DRA7xx SoCsAchieving Early CAN Response on DRA7xx DevicesDRA74x_75x/DRA72x Performance (Rev. A)Audio Post Processing Engine on Jacinto™ DRA7x Family of DevicesThe Implementation of YUV422 Output for SRVMMC DLL Tuning (Rev. B)Integrating AUTOSAR on TI SoC: FundamentalsECC/EDC on TDAxx (Rev. B)Tools and Techniques to Root Case Failures in Video Capture SubsystemSharing VPE Between VISIONSDK and PSDKLAAndroid Boot Optimization on DRA7xx Devices (Rev. A)Flashing Utility - mflashUsing Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A)Jacinto6 Spread Spectrum Clocking Configuration (Rev. A)Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B)A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B)Robust Rear-View Camera (RVC) App ReportUsing DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx DevicesSoftware Guidelines to EMIF/DDR3 Configuration on DRA7xx DevicesLinux Boot Time Optimizations on DRA7xx DevicesInterfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A)Early Splash Screen on DRA7x DevicesQuality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A)Gstreamer Migration GuidelinesFlashing Binaries to DRA7xx Factory Boards Using DFUTools and Techniques for Audio DebuggingDebugging Tools and Techniques With IPC3.xModifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A)Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device

    White paper:

    Jump Start Upgrading Your Digital Cluster Design with Jacinto 6 Platform (Rev. A)Revolutionize the automotive cockpitToday’s high-end infotainment soon becoming mainstream
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