Op-Amp Math Circuits: Sum, Difference, Integration and Differentiation

Author: lucy Lu | Published for icallin.com | Updated: November 8, 2026

Op-amp math circuits use closed-loop negative feedback networks around an operational amplifier to add signals, subtract common-mode offsets, integrate waveforms over time, or differentiate rapid transitions. Precision resistor ratios set the scaling weights in summing and difference amplifiers, while resistor-capacitor (RC) time constants govern the frequency-dependent behavior of integrators and differentiators. Turning textbook equations into reliable analog PCBs requires bounding the operating frequency band, matching passive component tolerances, and protecting high-impedance inverting nodes during layout.

Start with the negative-feedback and virtual-ground boundaries

All four classical op-amp math circuits rely on the amplifier operating linearly inside its closed negative-feedback loop. When the open-loop gain is high and the output stays within its linear compliance swing, negative feedback drives the inverting input (V-) to track the non-inverting input (V+), while high input impedance keeps input bias currents small relative to the feedback network currents.

When the non-inverting terminal connects to signal ground (or a mid-supply bias reference Vref in single-supply systems), the inverting summing node acts as a virtual ground. Because active feedback maintains that node voltage rather than a low-impedance copper return plane, routing unrelated return currents into the virtual-ground node—or letting the amplifier clip against its supply rails, exceed its slew-rate limit, or lose phase margin—immediately invalidates the ideal transfer equation.

Combine signals with an inverting summing amplifier

An inverting summing amplifier routes multiple input voltages (V1, V2, ..., Vn) through individual input resistors (R1, R2, ..., Rn) to the virtual-ground summing junction, with a single feedback resistor Rf closing the loop from the output to the inverting input. Because the virtual ground isolates the input branches from one another, each channel contributes independently according to its resistor ratio:

Vout = -Rf × (V1/R1 + V2/R2 + ... + Vn/Rn)

Each channel i is weighted by -Rf / Ri. Choosing equal input resistors (R1 = R2 = ... = Rn = R) weights every channel equally, and setting Rf = R produces an inverting unity-weighted sum (Vout = -(V1 + V2) for two inputs).

In hardware implementation, the driving source impedance (Rsource) of each upstream stage adds directly in series with its input resistor Ri, shifting the effective channel gain if Ri is not much larger than Rsource or buffered. Furthermore, as detailed in Texas Instruments' SBOA272 inverting summing amplifier design guide, adding more input channels lowers the parallel equivalent resistance at the summing node, which increases the circuit's noise gain (1 + Rf / Rparallel), amplifies input offset voltage, and reduces closed-loop bandwidth. Always verify worst-case output headroom when all input channels reach peak amplitude simultaneously.

Extract differential signals with resistor ratio matching

A four-resistor difference amplifier (subtractor) applies negative feedback while driving both amplifier inputs: input V1 connects through R1 to the inverting input with R2 providing feedback from Vout, while input V2 connects through R3 to the non-inverting input with R4 tied to the reference ground. When the upper and lower resistor ratios are matched such that:

R2 / R1 = R4 / R3 = k

the common-mode voltage cancels and the ideal output is proportional strictly to the input difference:

Vout = k × (V2 - V1)

In practice, common-mode rejection ratio (CMRR) depends heavily on resistor ratio matching and source-impedance balance. Even a 1% discrete resistor mismatch degrades DC common-mode rejection to roughly 34–40 dB at unity gain, allowing large common-mode noise to leak directly into the differential measurement. As explained in Analog Devices' Analog Dialogue analysis of difference amplifiers, unequal source impedances or asymmetric parasitic capacitance at the non-inverting node also unbalance the bridge across frequency. For precision current-shunt or sensor subtraction, specify matched monolithic resistor-network arrays (typically 0.1% or 0.01% ratio tolerance with tight TCR tracking) on the BOM, or step up to a three-op-amp instrumentation amplifier when high, balanced input impedance is required.

Bound the DC drift and bandwidth of an op-amp integrator

An ideal inverting op-amp integrator replaces the feedback resistor with a feedback capacitor C while feeding the input current through series resistor R. Because capacitor voltage is proportional to accumulated charge, the output integrates the input signal over time starting from initial condition Vout(t0):

Vout(t) = Vout(t0) - (1 / RC) × integral[Vin(t) dt, from t0 to t]

Feeding a constant DC voltage produces a linear output ramp, while a zero-centered square wave generates a triangle wave whose slope scales with 1 / (R × C).

However, an uncompensated ideal integrator acts as an open-loop amplifier at DC (XC -> infinity). In real hardware, microvolts of input offset voltage (Vos), nanoamps of input bias current (Ib), and capacitor leakage current continuously charge C until the amplifier output saturates against a supply rail. A practical design places a large bleed resistor Rf in parallel with C (or uses an active reset switch / servo loop), yielding the bounded transfer function:

H(s) = -(Rf / R) / (1 + s × Rf × C)

As shown in TI's CIRCUIT060027 practical integrator circuit, the circuit behaves as a true integrator at signal frequencies well above the lower corner fL = 1 / (2π × Rf × C) (often chosen at least 10× below the lowest operating frequency) and below the op-amp's unity-gain bandwidth limit, while limiting low-frequency DC gain to -Rf / R so the output never drifts into saturation.

Figure 1. Circuit topologies, ideal transfer equations, and compensated frequency-band controls for the four core op-amp math circuits.

Stabilize an op-amp differentiator against high-frequency noise

An ideal op-amp differentiator swaps the passive positions, placing capacitor C in the series input path and resistor Rf in the feedback path so output voltage tracks the input rate of change:

Vout(t) = -Rf × C × (dVin(t) / dt)

Under this relationship, a triangle-wave input produces a square-wave output, and rapid step edges generate sharp output pulses useful for edge detection and rate-of-change monitoring.

Because the ideal differentiator's reactance XC = 1 / (2πfC) drops with frequency, its gain rises at +20 dB/decade, amplifying high-frequency noise and introducing a 90° phase lag in the feedback network that erodes phase margin and causes severe ringing or oscillation. As demonstrated in TI's CIRCUIT060028 stabilized differentiator reference design, a production-ready circuit adds a small series input stopper resistor Rin (in series with C) and a small feedback compensation capacitor Cf (in parallel with Rf). Sizing Rin and Cf caps the high-frequency gain above the target differentiation band fH = 1 / (2π × Rin × C) and restores loop stability.

Preserve analog accuracy across BOM selection and PCB layout

Circuit topology	Ideal transfer relationship	Dominant hardware error source	Practical compensation & PCB check
Summing amplifier	`Vout = -Rf × Σ(Vi / Ri)`	Source impedance loading & higher noise gain	Buffer high-Z sources; check combined peak output swing
Difference amplifier	`Vout = k × (V2 - V1)` when `R2/R1 = R4/R3 = k`	Poor CMRR from resistor ratio or source mismatch	Use matched `0.1%` resistor networks; balance both paths
Op-amp integrator	`Vout = Vout(t0) - (1/RC) ∫Vin dt`	Output rail saturation from `Vos` and `Ib` DC drift	Add parallel `Rf` bleed resistor (`fL = 1/(2πRfC)`) + C0G cap
Op-amp differentiator	`Vout = -Rf × C × (dVin / dt)`	High-frequency noise amplification & loop oscillation

Table 1. Transfer equations, dominant hardware error mechanisms, and PCB/BOM design checks for the four op-amp math circuits.

Even well-calculated op-amp math circuits lose accuracy if passive component properties and PCB parasitics are overlooked during layout and procurement:

Keep the inverting summing junction compact: Place Rf, Cf, and input resistors immediately beside the op-amp's inverting pin (V-), and clear the ground plane directly beneath the V- pad if stray capacitance exceeds a few picofarads, since parasitic capacitance at V- creates a feedback pole that causes peaking.
Specify low-loss, low-drift BOM components: Use thin-film resistors (0.1% tolerance, ≤25 ppm/°C) for summing and difference networks, and specify C0G/NP0 ceramic or polypropylene film capacitors for integrators and differentiators—never Class II dielectrics like X7R or Y5V, whose capacitance shifts nonlinearly with applied DC bias voltage and causes harmonic distortion.
Protect power integrity and return paths: Place low-inductance local bypass capacitors right at the op-amp supply pins following PCB decoupling capacitor and current-loop guidelines, keep switching currents out of the analog reference using analog and digital ground return-path principles, and verify SPICE loop gain and headroom using circuit solver and model sanity checks before releasing fabrication files.

Frequently Asked Questions

Q1: Why does an op-amp integrator drift into saturation even when the input signal is zero?

Any real operational amplifier has a small input offset voltage (Vos) and input bias current (Ib). Because a pure feedback capacitor blocks DC feedback, those tiny error currents continuously charge the capacitor until Vout hits the positive or negative supply rail. Adding a parallel feedback resistor Rf (or a periodic MOSFET reset switch) provides a DC path that holds the quiescent operating point stable.

Q2: Can these four op-amp math circuits operate from a single positive power supply?

Yes. Instead of tying the non-inverting reference nodes to 0 V ground, bias them to a clean, low-impedance mid-supply reference voltage (such as Vref = VCC / 2 buffered by an op-amp or reference IC) and verify that input common-mode range and rail-to-rail output swing accommodate the full signal excursion around Vref.

Conclusion

Reliable op-amp math circuits depend on combining the right feedback topology with bounded frequency compensation, tight passive tolerances, and low-parasitic PCB layout. By specifying matched thin-film resistor ratios, C0G/film timing capacitors, DC bleed paths for integrators, and high-frequency stoppers for differentiators, engineering and procurement teams can take analog signal-conditioning stages cleanly from schematic calculation to assembled hardware.

Written by lucy Lu for icallin.com.