HCTL-2017 [Broadcom]

The HCTL-2021/2017 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2021/2017 consists of a quadrature decoder logic, a binary up/down state counter, and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2021/2017 contains 16-bit counter and provides TLL/CMOS compatible tri-state output buffers. Operation is specified for a temperature range from –40 to +85°C at clock frequencies up to 33MHz.