EP20K400GI655-3 [INTEL]

The APEX 20K family features MultiCore architecture integrating LUT logic for register-intensive functions, product-term logic for combinatorial-intensive functions, and embedded system blocks (ESB) for memory functions including FIFO, dual-port RAM, and CAM. It offers high density with up to 1.5 million gates, 51,840 logic elements, 442,368 RAM bits, and 3,456 macrocells. Devices support low-power operation with 1.8-V and 2.5-V supply voltages and MultiVolt I/O interface. Flexible clock management includes up to four PLLs with ClockLock, ClockBoost, and ClockShift features. Powerful I/O capabilities include PCI compliance, support for DDR SDRAM and ZBT SRAM, LVDS performance up to 840 Mbits per channel, and advanced I/O standards. Advanced interconnect structure provides fast, predictable delays with dedicated carry and cascade chains. Packaging options range from 144 to 1,020 pins in TQFP, PQFP, RQFP, BGA, FineLine BGA, and PGA packages.