KEY FEATURE
Double-data rate architecture, two data transfers per clock cycleBidirectional data strobes (DaS t. DaS c), These are transmitedlreceived with data to be used in capturing data at the recelvelDifferential clock inputs (CK tand CK c)
Differential data strobes (DQS t and DaS c)
Commands & addresses entered positive CK edges; data and data mask referenced to both edges of Das
2channel composition per die
8 internal banks for each channel
DMl Pin : DBl (Data Bus Inversion) when normal write and read operation, Data mask (DM) for masked write when DBl off-Counting # of DQ's 1 for masked write when DBl on
Burst Length: 16,32(0TF)
Burst Type: Sequential
Read & Write latency : Refer to Table 64 LPDDR4 AC Timing Table
Auto Precharae option for each burst access
Configurable Drive Strength
Refresh and Self Refresh Modes
Partial Array Self Refresh and Temperature Compensated Self Refresh
Write Leveling
CA Calibration
Internal VREF and VREF training
,FlFO based write/read training
MPC (Multi Purpose Command)
,LVSTL (Low Voltage Swing Terminated Logic) 10
VDD1NDD2/VDDQ:1.8V/1.1V/1.1V
.VSSQ Termination