EP2A25B652C7 [INTEL]

APEX II devices integrate high-speed differential I/O support using the True-LVDS interface. They incorporate LUT-based logic, product-term-based logic, memory, and high-speed I/O standards into one device. The architecture includes enhanced embedded system blocks (ESBs) for memory functions such as FIFO, Dual-Port+ RAM, and CAM. The devices support high-speed external memory interfaces including ZBT, QDR, DDR SRAM, and SDR/DDR SDRAM. They offer up to 5,250,000 system gates and up to 67,200 logic elements. The devices feature MultiVolt I/O support for 1.5V, 1.8V, 2.5V, and 3.3V interfaces, and configuration at 3.3V and 2.5V or 1.8V. The True-LVDS interface supports up to 1 Gbps, and Flexible-LVDS supports up to 400 Mbps. The devices also include general-purpose PLLs for clock management and support for various I/O standards including PCI, PCI-X, LVDS, and HyperTransport.