EPM7064AEFC100-4N [INTEL]

The MAX 7000A family includes high-performance, EEPROM-based programmable logic devices (PLDs) built on the second-generation MAX architecture. These devices operate at 3.3V and offer in-system programmability (ISP) via a JTAG interface, boundary-scan test (BST) compliance, and support for JEDEC Jam STAPL. Key features include MultiVolt I/O interface (3.3V core with 5.0V/3.3V/2.5V I/O compatibility), a range of package options (TQFP, PQFP, BGA, FineLine BGA, PLCC), hot-socketing support, programmable interconnect array for fast performance, PCI compatibility, programmable slew-rate control, open-drain output, programmable macrocell registers, power-saving mode for up to 50% power reduction, configurable expander product-term distribution (up to 32 product terms per macrocell), programmable security bit, and dedicated fast input paths. The devices are supported by Altera development systems and are suitable for a variety of logic integration tasks.