EPM7128BFC100-4 [INTEL]

High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX) architecture. Pin-compatible with 5.0-V MAX7000S and 3.3-V MAX7000A families. Features include 600 to 10,000 usable gates, 3.5-ns pin-to-pin delays, counter frequencies exceeding 303.0 MHz, advanced 2.5-V in-system programmability (ISP) via JTAG, MultiVolt I/O interface (2.5-V core with 3.3-V/2.5-V/1.8-V I/O compatibility), programmable power-saving mode for ≥50% power reduction, fast input setup times, support for advanced I/O standards (SSTL-2/3, GTL+), bus-hold option, PCI compatibility, programmable security bit, boundary-scan test circuitry (IEEE 1149.1), hot-socketing support, and programmable ground pins. Architecture includes configurable expander product-term distribution (up to 32 product terms per macrocell), programmable macrocell registers, two global clocks, and 6-10 output enables.