EPM7256BFC169-5 [INTEL]

MAX 7000B devices are EEPROM-based programmable logic devices (PLDs) built on the second-generation MAX architecture. They operate with a 2.5-V supply voltage and provide 600 to 10,000 usable gates, in-system programmability (ISP) via JTAG, pin-to-pin delays as fast as 3.5 ns, and counter frequencies up to 303.0 MHz. The devices feature MultiVolt I/O interface for compatibility with 3.3V, 2.5V, and 1.8V logic levels, programmable power-saving mode, fast input setup times, support for advanced I/O standards (SSTL-2, SSTL-3, GTL+, PCI), bus-hold option, open-drain output, programmable security bit, boundary-scan test (IEEE 1149.1), hot-socketing support, and programmable ground pins. The architecture includes programmable interconnect array (PIA) for fast predictable performance, configurable expander product-term distribution (up to 32 product terms per macrocell), programmable macrocell registers with clear, preset, clock, clock enable, two global clock signals, programmable power-up states, and 6 to 10 output enable signals. Available in a variety of packages including PLCC, TQFP, PQFP, BGA, FineLine BGA, and Ultra FineLine BGA. Supported by Altera development systems (MAX+PLUS II, Quartus) and industry-standard EDA tools.