EPM7064TC44-12 [INTEL]

The MAX 7000 family is a high-density, high-performance PLD family based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, it provides 600 to 5,000 usable gates, in-system programmability (ISP) via JTAG, pin-to-pin delays as fast as 5 ns, and counter frequencies up to 175.4 MHz. Devices support 5.0-V operation with MultiVolt I/O interface for 3.3-V or 5.0-V compatibility, and include enhanced features in MAX7000E and MAX7000S devices such as additional global clocking, output enable controls, and programmable power-saving modes. Available in various packages including PLCC, PGA, PQFP, RQFP, and TQFP.