EPM7064STC100-5N [Altera]

The MAX 7000 family is a high-density, high-performance PLD family based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, these EEPROM-based devices provide 600 to 5,000 usable gates, ISP through JTAG interface, pin-to-pin delays as fast as 5 ns, and counter speeds up to 175.4 MHz. They include 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices, with enhanced features such as JTAG boundary-scan test, MultiVolt I/O interface for 3.3-V or 5.0-V operation, programmable power-saving mode, security bit, and configurable macrocells with up to 32 product terms. Available in various packages including PLCC, PGA, PQFP, RQFP, and TQFP, and supported by Altera's development systems for design entry, compilation, simulation, and programming.