EPM7128BFC256-4 [Altera]

High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX) architecture. Pin-compatible with MAX7000S and MAX7000A families. High-density PLDs ranging from 600 to 10,000 usable gates. 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz. Advanced 2.5-V in-system programmability (ISP) via JTAG. MultiVolt I/O interface: 2.5V core, I/O pins compatible with 3.3V, 2.5V, 1.8V logic levels. Programmable power-saving mode for 50% or greater power reduction. Fast input setup times via dedicated path from I/O pin to macrocell registers. Support for advanced I/O standards (SSTL-2, SSTL-3, GTL+). Bus-hold option, PCI compatible, programmable slew-rate control. Open-drain output option. Programmable security bit. Built-in boundary-scan test (IEEE 1149.1). Hot-socketing operation. Programmable ground pins. Programmable interconnect array (PIA) for fast, predictable performance. Configurable expander product-term distribution (up to 32 product terms per macrocell). Programmable macrocell registers with clear, preset, clock, clock enable. Two global clock signals with inversion. Programmable power-up states for macrocell registers. 6 to 10 pin- or logic-driven output enable signals. Various package options (TQFP, PQFP, BGA, PLCC, etc.). Software support (MAX+PLUS II, Quartus, EDIF, VHDL, Verilog, etc.).