EPM7256BUC169-10 [Altera]

The MAX 7000B family features high-performance 2.5-V CMOS EEPROM-based programmable logic devices built on second-generation Multiple Array MatriX (MAX) architecture. These devices offer densities from 600 to 10,000 usable gates with 3.5-ns pin-to-pin delays and counter frequencies exceeding 303.0 MHz. They include advanced 2.5-V in-system programmability (ISP) via JTAG interface, MultiVolt I/O interface supporting 3.3-V, 2.5-V, and 1.8-V logic levels, programmable power-saving mode for up to 50% power reduction, and fast input setup times through dedicated paths. Additional features include support for advanced I/O standards (SSTL-2, SSTL-3, GTL+), bus-hold option, PCI compatibility, programmable security bit, boundary-scan test circuitry (IEEE 1149.1), hot-socketing operation, and programmable ground pins. The architecture incorporates programmable interconnect array (PIA) for fast routing, configurable expander product-term distribution (up to 32 product terms per macrocell), programmable macrocell registers with independent controls, two global clock signals, and programmable power-up states. Devices are available in various packages including TQFP, PQFP, BGA, FineLine BGA, Ultra FineLine BGA, and PLCC.