EPM7256SRC208-7 [Altera]

High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX architecture. Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices. Logic densities from 600 to 5,000 usable gates. Pin-to-pin delays as fast as 5 ns, counter frequencies up to 175.4 MHz. PCI-compliant devices available. Features include programmable power-saving mode (over 50% reduction per macrocell), programmable security bit, MultiVolt I/O interface (3.3-V or 5.0-V operation, not in 44-pin packages), and enhanced features in MAX7000E and MAX7000S (additional global clocking, output enables, fast input registers, slew-rate control). Available in PLCC, PGA, PQFP, RQFP, TQFP packages.