NG80960JS25 [Altera]

The 80960Jx microprocessors are high-performance 32-bit embedded processors with code compatibility across the 80960Jx family. They feature a load/store programming model, sixteen 32-bit global registers, sixteen 32-bit local registers (8 sets), and nine addressing modes. The architecture includes a two-way set associative instruction cache (sizes vary by model: 2 KB for 80960JA, 4 KB for 80960JF/JD, 16 KB for 80960JS/JC/JT), a direct-mapped data cache (1 KB for 80960JA, 2 KB for 80960JF/JD, 4 KB for 80960JS/JC/JT), and an on-chip stack frame cache. They support a high-bandwidth 32-bit multiplexed address/data burst bus with programmable memory configuration, selectable bus widths (8-, 16-, 32-bit), unaligned accesses, and big or little endian byte ordering. Additional features include a high-speed interrupt controller with 31 programmable priorities, eight maskable pins plus NMI#, up to 240 vectors in expanded mode, two independent 32-bit on-chip timers with clock prescaling, halt mode for low power, and IEEE 1149.1 (JTAG) boundary scan compatibility. The processors operate at 3.3V supply with 5V tolerant inputs and TTL compatible outputs.