DIVIDE-E3-UT [LATTICE]

A one-clock divider IP core that completes one integer division per clock cycle. Supports signed or unsigned numerator and denominator with data widths from 4 to 64 bits. Features include forced positive remainder, configurable output latency (1-64 cycles), and optional clock enable and data valid ports. Designed for Lattice FPGA families including LatticeECP3, LatticeECP2M, LatticeECP2, and LatticeXP2.