CORE1553BBC-AR [MICROSEMI]

The Core1553BBC is a complete MIL-STD-1553B Bus Controller core that reads message descriptor blocks from memory and generates messages for transmission on the 1553B bus. It consists of five main blocks: 1553B encoder, 1553B decoder, protocol controller, CPU interface, and backend interface. The core supports synchronous or asynchronous memory devices, provides direct CPU access to memory, and interfaces with standard 1553B transceivers. It features fully automated message scheduling with frame support, conditional branching, sub-routines, variable inter-message gaps, RT response times, real-time clock for message scheduling, and asynchronous message support. The backend interface allows connection to external memory up to 128kbytes and supports standard bus request/grant protocols with WAIT input for slow memory devices.