DSPIC33CK256MC506-E/PTVAO [Microchip]

Microchip’s dsPIC33CK256MC50X family of Digital Signal Controllers (DSCs) features a single 100 Mhz dsPIC^® DSC core with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of motor control, high-performance, general embedded and robust applications in automotive, industrial, medical and consumer segments.

In the motor control segment, this family is well suited for cost competitive automotive, consumer and industrial applications. The dsPIC33CK256MC50X family of DSCs is ideal for the control of BLDC, PMSM, ACIM, SR and stepper motors. The high level of peripheral integration on the dsPIC33CK256MC50X DSCs enables applications to implement power factor correction (PFC) and Field Oriented Motor Control (FOC) using a single DSC.

This dsPIC33CK cost-effective family supporting offering core-independent touch capabilities, is well suited for complex touch designs that require up to 256KB flash, functional safety, security, CAN/CAN FD and high level of various function integration.

Loaded with advanced analog peripherals such as high-performance 12-bit ADCs and 12-bit DACs, high-speed analog comparators, and op amps, dsPIC33CK256MC50X family of DSCs provides simple-to-use smart sensor interfaces for various electronic sensing applications. The rich feature set and the 150°C high-temperature rating available on this DSC family make it a very good fit for automotive sensors and industrial automation.

The Functional Safety Ready dsPIC33CK product family has many features and a comprehensive safety ecosystem that help simplify the design of safety-critical applications and achieve functional safety certification. Learn more about Functional Safety Readiness including hardware, software, and supporting collateral, visit https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/dspic-dscs/functional-safety.

Operating Conditions
• 3.0 V to 3.6 V
• -40ºC to +125ºC, DC to 100 MIPS
• -40ºC to +150ºC, DC to 70 MIPS

dsPIC33CK DSC Core and Memory
• Up to 256 KBytes of Program Flash with ECC
• Up to 32 KBytes of Data SRAM with Memory Built in Self-Test (MBIST)
• Modified Harvard architecture with 16-bit data and 24-bit instructions
• Code efficient (C and Assembly) CPU architecture designed for real-time applications
• Sixteen 16-bit working registers
• Four sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
• Single-cycle, mixed-sign 32-bit multiplication
• Fast 6-cycle hardware 32/16 and 16/16 DIV
• Dual 40-bit fixed point Accumulators (ACC) for DSP operations
• Single-cycle MAC/MPY with dual data fetch and result write-back
• Zero overhead looping support

Core Independent Touch
• Uses Peripheral Trigger Generator (PTG) and High-speed ADCs
• Ready-to-use touch library support in MPLAB Code Configurator (MCC)

Functional Safety Support (ISO 26262 and IEC 61508)
• ISO 26262 compliant development
• ASIL B automotive safety applications – ISO 26262
• SIL 2 industrial safety applications – IEC 61508
• ISO 26262 and IEC 61508 Functional Safety Packages

Embedded Security
• CodeGuard security together with Flash OTP by ICSP Write Inhibit enables implementing Immutable Secure Boot
• Flash OTP by ICSP Write Inhibit to configure the entire Flash as OTP
• User OTP
• Enables implementing robust security use cases together with CryptoAuthentication and CryptoAutomotive devices such as:
• Secure Boot
• Secure Firmware Upgrade
• Secure Communication
• Node Authentication and more

AUTOSAR-Ready DSC supporting
• AUTOSAR (4.3.x)
• ASIL B- and ASPICE-compliant MCAL drivers
• ISO 26262 Functional Safety and Automotive Security

High-Speed PWM Module
• Four independent PWM pairs (Eight total outputs) with up to 2 ns resolution
• Dead-time insertion for rising and falling edges and dead-time compensation support
• Clock chopping for high-frequency operation
• Fault and current limit inputs
• Flexible trigger configuration for ADC triggering

Advanced Analog Features
• 12-bit 3.5 MSPS ADC Module
• Up to 20 ADC input channels (depending on package)
• Four digital comparators for reducing CPU overhead
• Four oversampling filers up to 256x for increased resolution (up to 16-bits)
• Two analog comparators (15ns) with dedicated 12-bit DAC with hardware slope compensation and One DAC buffer output
• Up to three op amps with internal connection to ADC Module, 20 MHz GBW, ±1 mV offset voltage and 40 v/μs slew rate

Timer/Counters/Output Compare/Input Capture
• Nine 16-bit timer/counters (or four 32-bit)
• 4 PWM or Output Compare (OC) outputs
• 4 Input Captures (IC) pins or internal connections from the CLC or Comparator Modules
• Peripheral Trigger Generator (PTG) for scheduling complex sequences
• One Quadrature Encoder Interface (QEI) Modules for optical encoder support

Communication Interfaces
• Three UARTs (15 Mbps) with automated protocol handling for LIN/J2602 and DMX
• Two 4-wire SPI/I2S up to 40 MHz with dedicated pins
• One I2C Module (up to 1 Mbps) with SMBus support
• CAN Flexible Data Rate (CAN-FD) Module ('50x devices only)
• One Single-Edge Nibble Transmission (SENT) Modules for sensor interfacing
• Four DMA channels supporting data transfers

Special Features
• Four Configurable Logic Cell (CLC) Modules with user defined logic gate circuits
• Programmable Pin Select (PPS) for peripheral pin function mapping
• On-chip temperature sensor with direct ADC Module connection
• 256 Bytes of One-Time-Programmable (OTP) Memory and 120-bit Unique Device Identifier (UDID)

Clock and Power Management
• On-chip 8 MHz Fast RC (FRC)
• Programmable PLLs with external oscillator clock sources and Reference Clock Output (REFO)
• Fail-Safe Clock Monitor (FSCM) with 8 MHz Back-up Fast RC (BFRC) oscillator
• Low-Power management modes - Sleep, Idle and Doze
• Integrated Power-on Reset (POR) and Brown-Out Reset (BOR)

Debugger Development Support
• In-Circuit and in application programming and debug support (ICSP)
• On-chip debug with 3 complex and 5 simple breakpoints
• IEEE 1149.2 (JTAG) boundary scan support

Safety Features
• Dead-Man Timer (DMT) safety feature clocked by instruction fetches
• Windowed Watch Dog Timer (WWDT)
• CodeGuard™ Security for Program FLASH
• FLASH with ECC and Fault Injection testing feature
• Flash OTP by ICSP™ write inhibit
• Memory Built in Self-Test (MBIST)
• Clock Monitor with multiple redundant clock sources
• Programmable Cyclic Redundancy Check (CRC)
• Hardware traps
• SFR locks
• Shadow working registers
• PWM Fault Management
• cap-less on-chip LDO
• I/O Port read-back