LAN9662/9MX [Microchip]

The LAN9662 is part of a family (LAN966x) of compact and cost-effective, multi-port Gigabit AVB/TSN Ethernet Switches with two integrated 10/100/1000BASE-T PHYs and a 600 MHz ARM Cortex A7 CPU subsystem. The LAN9662 includes four ports in addition to an Industrial Ethernet (IE) protocol Real-Time Engine (RTE) suited for meshed and daisy-chained low latency operation.

In addition to the two integrated PHYs, the LAN9662 supports up to 2 RGMII/RMII, up to 2 1000BASE-X/SerDes/2.5GBASE-X/KX, and up to 1 Quad-SGMII/Quad-USGMII interfaces.

Support for 802.3bz 2.5G Ethernet via SGMII+

The LAN9662 is designed for PROFINET RT, PROFINET v2.4 TSN, and OPC UA PubSub automation networks at the field level, supporting asynchronous and low cycle time synchronous operation. With its four Gigabit Ethernet ports in combination with the Industrial Ethernet Real-Time Engine, low latency chain, tree, and meshed topologies are possible for PROFINET and OPC UA PubSub, while also supporting low latency cut-through daisy-chains for OPC UA PubSub summation frames (aka aggregation frame and modify-on-the-fly).

To obtain the LAN9662 register file, click here.

VSC6803 (MESA) API and associated documentation is available here.

Switchdev support available via Linux mainline. BSP documentation is available here.

MERA (Microchip Ethernet Real Time Engine API) and P-NET are available here and here.

TFA (ARM Trusted Firmware) v2.8.17 is available here.

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