MCP3913A1-E/SS [Microchip]

The MCP3913 device is a 3V six-channel Analog Front End (AFE, containing six simultaneous sampling delta-sigma ADCs, six PGAs, phase delay compensation block, low-drift internal voltage reference, digital offset and gain error calibration registers, and high-speed 20 MHz SPI compatible serial interface. The MCP3913 ADCs are fully configurable, with features such as: 16/24-bit resolution, Oversampling Ratio (OSR) from 32 to 4096, gain from 1x to 32x, independent Shutdown and Reset, dithering and auto-zeroing. The MCP3913 AFE includes advanced security features to secure the communications and the configuration settings, such as a CRC-16 checksum on both serial data outputs and static register map configuration. It also includes a register-map lock through an 8-bit secure key to stop unwanted write commands from processing. The MCP3913 AFE is capable of interfacing with a variety of voltage and current sensors, including shunts, current transformers, Rogowski coils and Hall-effect sensors.

The MCP391x portfolio of Analog Front Ends feature performance and functionality which makes them appropriate for use in designs targeted to meet the following industry standards for smart metering applications: IEC62053-11, IEC62053-21, IEC62053-22, ANSI C12.20. In such designs, the MCP391x portfolio can be paired with either MCUs/MPUs which are running a metrology engine, or standard (non-Metrology) MCUs/MPUs.

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• Six Simultaneous Sampling 24-bit Delta-Sigma ADCs
• 94.5 dB SINAD, -107 dBc Total Harmonic Distortion (THD) (up to 35th Harmonic), 112 dBFS SFDR for Each Channel
• Enables 0.1% Typical Active Power Measurement Error over a 10,000:1 Dynamic Range
• Advanced Security Features: - 16-bit Cyclic Redundancy Check (CRC) checksum - 16-bit CRC checksum and interrupt alert for register map configuration - Register map lock with 8-bit secure key
• Programmable Data Rate up to 125 ksps
• Oversampling Ratio up to 4096
• Ultra-Low Power Shutdown Mode with < 10 µA
• -122 dB Crosstalk between Channels
• Differential Voltage Reference Input Pins
• High Gain Programmable-Gain Amplifier (PGA) on Each Channel (up to 32 V/V)
• Phase Delay Compensation with 1 µs Time Resolution
• Separate Data Ready Pin for Easy Synchronization
• Individual 24-bit Digital Offset and Gain Error Correction for Each Channel
• High-Speed 20 MHz Serial Peripheral Interface (SPI) with Mode 0,0 and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum Communication Time
• Available in a 28-lead SSOP and 40-lead UQFN Package
• AEC-Q100 Grade 1