PIC18F56Q24-E/PT [Microchip]

The PIC18-Q24 microcontroller family offers a range of features and capabilities for sensor-interfacing, real-time control, and communication applications. This family introduces the Programming and Debugging Interface Disable module to increase code and data protection. It includes a Multi-Voltage I/O interface, a 10-bit Analog-to-Digital Converter with Computation, and an 8-bit Signal Routing Port module for interconnecting digital peripherals. This family of devices also has additional features like a Vectored Interrupt Controller, DMA capabilities, various communication protocols (UART, SPI, I2C), and memory features such as Memory Access Partition and Device Information Area.

Multi-Voltage I/O (MVIO):
• MVIO-powered pins support operation from 1.62V to 5.5V
• This domain is independent of the main VDD voltage level
• Voltage monitoring on the additional voltage domain with programmable trip points

Programming and Debugging Interface Disable (PDID):
• The ICSP interface can be disabled to prevent external memory access or modifications.

Vectored Interrupt (VI) Capability - Faster interrupt response time
• Selectable high/low priority
• Fixed interrupt latency of three instruction cycles
• Programmable vector table base address
• Backwards compatible with previous interrupt capabilities

Memory Access Partition (MAP): The Program Flash Memory can be partitioned into:
• Application Block
• Boot Block
• Storage Area Flash (SAF) Block with SAFLOCK to prevent modifications

Programming/Debugging Features:
• Programming and Debugging Interface Disable (PDID)
• In-Circuit Serial Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) with Three Breakpoints via Two Pins
• Debug Integrated On-Chip

Four Direct Memory Access (DMA) Controllers

Analog-to-Digital Converter with Computation (ADCC):
• 10-bit ADC with computation with up to 300ksps
• Up to 30 external channels
• Automated math functions on input signals such as averaging, filter calculations, oversampling and threshold comparison
• Operates in Sleep
• Five internal analog channels
• Hardware Capacitive Voltage Divider (CVD) Support:
• Automates touch sampling and reduces software size and CPU usage

8-Bit Digital-to-Analog Converter (DAC):
• Buffered output available on two I/O pins
• Internal connections to ADC and Comparators

Two High-Speed Comparators (CMP):
• Configurable power vs. speed modes
• Configurable output polarity
• External output via Peripheral Pin Select

Two Zero-Cross Detect (ZCD):
• Detect when AC signal on pin crosses ground

Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels
• Voltage Reference:
• Internal connections to ADC, Comparator, and DAC

Three 16-bit dual PWMs provide six PWM outputs

UART with hardware support for LIN/DMX
• DMA compatible
• Asynchronous UART, RS-232, RS-485 compatible
• Programmable 1, 1.5, 2 stop bits

Two SPI modules:
• Configurable length bytes
• Arbitrary length data packets
• Transmit-without-Receive and Receive-without-transmit option
• Transfer byte counter
• Separate transmit and receive buffers with 2-byte FIFO and DMA capabilities

Two I2C module, SMBus, PMBus™ Compatible:
• 7-bit and 10-bit addressing modes with address masking modes
• Dedicated address, transmit and receive buffers and DMA capabilities
• I2C, SMBus 2.0 and SMBus 3.0, and 1.8V input level selections
• Multi-Master mode, including self-addressing

Device Information Area (DIA) Stores:
• Temperature Indicator factory calibrated data
• Fixed Voltage Reference measurement data
• Microchip Unique Identifier

Low Power Mode Features:
• Sleep: < 1μA typical @ 3V
• Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower)
• Idle: CPU Halted While Peripherals Operate
• Sleep: Lowest Power Consumption

Peripheral Module Disable (PMD):
• Selectively disable the hardware module to minimize active power consumption of unused peripherals