EVSTGAP2GSN [STMicroelectronics]

The EVSTGAP2GSN is a half bridge evaluation board designed to evaluate the STGAP2GSN isolated single gate driver.

The gate driver is characterized by 2 A source and 3 A sink capability and rail-to-rail outputs, making the device also suitable for mid and high power inverter applications such as power conversion and motor driver inverters in industrial applications.

The device allows to independently optimize turn-on and turn-off by using dedicated gate resistors.

The device integrates protection functions including thermal shutdown and UVLO with optimized level for enhancement-mode GaN transistors, which enables easy design high efficiency and reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction.

The device allows implementing negative gate driving, and the on board isolated DC-DC converters allows working with optimized driving voltage for e-mode GaN transistors.

The EVSTGAP2GSN board allows evaluating all the STGAP2GSN features driving the SGT120R65AL 75 mΩ, 650 V e-Mode GaN transistors.

The board components are easy to access and modify to make driver performance evaluation easier under different application conditions and fine adjustment of final application components.

• Board
  • Half bridge configuration, high voltage rail
    up to 650 V
  • SGT120R65AL: 650 V, 75 mOhm typ., 15 A, e-mode
    PowerGaN transistor
  • Negative
    gate driving
  • On board isolated DC-DC converters to supply high-side and
    low-side gate drivers, fed by VAUX = 5 V, with 1.5
    kV maximum isolation
  • VDD logic supplied by on-board 3.3 V or VAUX = 5 V
  • Easy jumper selection of driving voltage configuration:
    +6/0 V; +6/-3 V
• Device
  • 1700 V functional isolation
  • Driver current capability: 2 A / 3 A source/sink @ 25 °C,
    VH = 6 V
  • Separate sink and source for easy gate driving
    configuration
  • Input-output propagation delay: 45 ns
  • UVLO function optimized for GaN
  • Gate driving voltage up to 15 V
  • 3.3 V, 5 V TTL/CMOS inputs with hysteresis
  • Temperature shut down protection