STA8100GATR [STMicroelectronics]

The STA8100GA is part of the TeseoV family. The STA8100GA is a multiband multiconstellation positioning receiver IC able to manage all the GNSS constellations such as GPS, Galileo, Glonass, BeiDou, NAVIC (former IRNSS), and QZSS in the L1, L2, L5, and E6 frequency bands. The STA8100GA supports L2 and E6 baseband signal processing. The RF reception of the L2 and E6 signals requires an external front-end IC (STA5635A). The STA8100GAD comes with STMicroelectronics's dead reckoning firmware called TESEO-DRAW.

• AEC-Q100 qualified
• TESEO-DRAW (dead reckoning automotive way) is supported on STA8100GAD only
• Code phase, carrier phase, and doppler frequency measurement
• Antenna sensing
• Notch filter for antijamming
• ESD: 2 kV (HBM) and 500 V (CDM)
• Automotive grade: 105 °C
• 81-ball, 8 × 8 × 1.7 mm, 0.8 mm pitch, LFBGA package
• Core
  • Arm^® Cortex^®‑M7 core:
    • Maximum clock frequency 314 MHz
    • 16 KB instruction cache and 16 KB data cache
    • 64 KB instruction TCM and 384 KB data TCM core clock speed
    • Nested vector interrupt controller
    • JTAG debugging capability
    • 256 Kbyte system RAM
    
    
• Memory interfaces
  • SFC (octal/quad serial flash memory controller, SDR)
  • SD multimedia card
• GNSS features
  • STMicroelectronics's 5^th generation positioning receiver with 80 tracking channels and 4 fast acquisition channels compatible with 6 constellations: GPS, Galileo, GLONASS, BeiDou, QZSS, and NAVIC (former IRNSS)
  • Dual band L1 and L5 single chip solution
  • Triple band capability with external RF STA5635A
  • L-band raw correction data reception
  • SBAS systems: WAAS, EGNOS, MSAS, GAGAN, and BeiDou
• Communication interfaces
  • PPS output
  • 3 × UART
  • Synchronous serial port (SPI supported)
  • I²C
  • 2 × multimode serial interfaces
  • 2 × CAN controllers
  • USB 2.0 full speed (12 Mbit/s) with integrated physical layer transceiver
• Core peripherals
  • 32-channel DMA
  • 32 kHz oscillator real-time clock
  • 2 × multitimer units
  • Watchdog timer
  • 1 × extended function timers
• Power management unit
  • Separate power-supply domains and on-chip LDO and high-voltage/low-voltage monitors:
    • Backup voltage domain: 1.62 V to 3.6 V with LDO for the always-on core supply and high-voltage/low-voltage detectors, and a dedicated IO-ring0
    • Main voltage domain: 1.62 V to 3.6 V with LDO for the switchable logic domain and high-voltage/low-voltage detectors for operation at 85 °C maximum ambient temperature1.2 V ± 5% external voltage supply for operation at 105 °C maximum ambient temperature
    • Separate RF domain with dedicated LDO
    • IO-ring1 1.8 or 3.3 V capable, with a dedicated 1.8 V LDO
    • IO-ring2 3.3 V ±10 % capable
    • Fail-safe GPIOs available