The STGAP2SA is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry.

The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device has a single output pin and Miller CLAMP function that prevents gate spikes during fast commutations in half-bridge topologies. This configuration provides high flexibility and bill of material reduction for external components. 

The device integrates protection functions: UVLO with optimized value for Si MOSFETs and thermal shut down are included to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay is less than 60 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption.

• AEC-Q100 qualified
• High voltage rail up to 1200 V
• Driver current capability: 4 A sink/source @25°C
• 100 V/ns Common Mode Transient Immunity (CMTI)
• Overall input-output propagation delay: 60 ns
• Rail-to-rail outputs
• 4 A Miller CLAMP dedicated pin
• UVLO function
• Gate driving voltage up to 26 V
• 3.3 V, 5 V TTL/CMOS inputs with hysteresis
• Temperature shut-down protection
• Standby function
• Narrow body SO-8N package
• UL 1577 recognized