The STM32MP133C/F devices are based on the high-performance Arm^® Cortex^®-A7 32-bit RISC core operating at up to 1 GHz. The Cortex^®-A7 processor includes a 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache and a 128-Kbyte level2 cache. The Cortex^®-A7 processor is a very energy-efficient application processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20 % more single thread performance than the Cortex^®-A5 and provides similar performance to the Cortex^®­A9.

The Cortex^®-A7 incorporates all features of the high-performance Cortex^®-A15 and Cortex^®-A17 processors, including virtualization support in hardware, NEON™, and 128-bit AMBA^®4 AXI bus interface.

The STM32MP133C/F devices provide an external SDRAM interface supporting external memories up to 8-Gbit density (1 Gbyte), 16-bit LPDDR2/LPDDR3 or DDR3/DDR3L up to 533 MHz.

The STM32MP133C/F devices incorporate high-speed embedded memories with 168 Kbytes of internal SRAM (including 128 Kbytes of AXI SYSRAM, two banks of 8 Kbytes and one bank of 16 Kbytes securable AHB SRAM, and 8 Kbytes of SRAM in Backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, and a 64-bit multi-layer AXI interconnect supporting internal and external memories access.

All the devices offer two ADCs, a low-power secured RTC, ten general-purpose 16-bit timers, two 32-bit timers, two PWM timers for motor control, five low-power timers, a secured true random number generator (RNG), and an advanced secured cryptographic acceleration cell. The devices support two digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces.