STM32MP135AAE3 [STMicroelectronics]

The STM32MP135A/D devices are based on the high-performance Arm^® Cortex^®-A7 32-bit RISC core operating at up to 1 GHz. The Cortex^®-A7 processor includes a 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache and a 128-Kbyte level2 cache. The Cortex^®-A7 processor is a very energy-efficient application processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20 % more single thread performance than the Cortex^®-A5 and provides similar performance to the Cortex^®­A9.

The Cortex^®-A7 incorporates all features of the high-performance Cortex^®-A15 and Cortex^®-A17 processors, including virtualization support in hardware, NEON™, and 128-bit AMBA^®4 AXI bus interface.

The STM32MP135A/D devices provide an external SDRAM interface supporting external memories up to 8-Gbit density (1 Gbyte), 16-bit LPDDR2/LPDDR3 or DDR3/DDR3L up to 533 MHz.

The STM32MP135A/D devices incorporate high-speed embedded memories with 168 Kbytes of internal SRAM (including 128 Kbytes of AXI SYSRAM, two banks of 8 Kbytes and one bank of 16 Kbytes securable AHB SRAM, and 8 Kbytes of SRAM in Backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, and a 64-bit multi-layer AXI interconnect supporting internal and external memories access.

All the devices offer two ADCs, a low-power secured RTC, ten general-purpose 16-bit timers, two 32-bit timers, two PWM timers for motor control, five low-power timers, a secured true random number generator (RNG). The devices support two digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces.

• Includes ST state-of-the-art patented technology
• Core
  • 32-bit Arm^® Cortex^®-A7
    
    • L1 32-Kbyte I / 32-Kbyte D
    
    
    • 128-Kbyte unified level 2 cache
    
    
    • Arm^® NEON™ and Arm^® TrustZone^®
    
    
• Memories
  • External DDR memory up to 1 Gbyte
    
    • up to LPDDR2/LPDDR3-1066 16-bit
    
    
    • up to DDR3/DDR3L-1066 16-bit
    
    
  • 168 Kbytes of internal SRAM: 128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain
    
  • Dual Quad-SPI memory interface
    
  • Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC
    
• Security/safety
  • TrustZone^® peripherals, 12 x tamper pins including 5 x active tampers
    
  • Temperature, voltage, frequency and 32 kHz monitoring
    
• Reset and power management
  • 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)
    
  • POR, PDR, PVD and BOR
    
  • On-chip LDOs (USB 1.8 V, 1.1 V)
    
  • Backup regulator (~0.9 V)
    
  • Internal temperature sensors
    
  • Low-power modes: Sleep, Stop, LPLV-Stop, LPLV­Stop2 and Standby
    
  • DDR retention in Standby mode
    
  • Controls for PMIC companion chip
    
• Clock management
  • Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator
    
  • External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
    
  • 4 × PLLs with fractional mode
    
• General-purpose input/outputs
  • Up to 135 secure I/O ports with interrupt capability
    
  • Up to 6 wakeup
    
• Interconnect matrix
  • 2 bus matrices
    
    • 64-bit Arm^® AMBA^® AXI interconnect, up to 266 MHz
    
    
    • 32-bit Arm^® AMBA^® AHB interconnect, up to 209 MHz
    
    
• 4 DMA controllers to unload the CPU
  • 56 physical channels in total
    
  • 1 x high-speed general-purpose master direct memory access controller (MDMA)
    
  • 3 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management
    
• Up to 30 communication peripherals
  • 5 × I²C FM+ (1 Mbit/s, SMBus/PMBus™)
    
  • 4 x UART + 4 x USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
    
  • 5 × SPI (50 Mbit/s, including 4 with full-duplex I²S audio class accuracy via internal audio PLL or external clock)
    
  • 2 × SAI (stereo audio: I²S, PDM, SPDIF Tx)
    
  • SPDIF Rx with 4 inputs
    
  • 2 × SDMMC up to 8 bits (SD/e•MMC™/SDIO)
    
  • 2 × CAN controllers supporting CAN FD protocol
    
  • 2 × USB 2.0 high-speed Host
    
    • or 1 × USB 2.0 high-speed Host+ 1 × USB 2.0 high-speed OTG simultaneously
    
    
  • 2 x Ethernet MAC/GMAC
    
    • IEEE 1588v2 hardware, MII/RMII/RGMII
    
    
  • 8- to 16-bit camera interface, 3 Mpix @30 fps or 5Mpix @15 fps in color or monochrome with pixel clock @120 MHz (max freq)
    
• 6 analog peripherals
  • 2 × ADCs with 12-bit max. resolution up to 5 Msps
    
  • 1 x temperature sensor
    
  • 1 x digital filter for sigma-delta modulator (DFSDM) with 4 channels and 2 filters
    
  • Internal or external ADC reference V_REF+
    
• Graphics
  • LCD-TFT controller, up to 24-bit // RGB888
    
    • up to WXGA (1366 × 768) @60 fps or up to Full HD (1920 x 1080) @ 30 fps
    
    
    • pixel clock up to 90 MHz
    
    
    • two layers (incl. 1 secured) with programmable color LUT
    
    
• Up to 24 timers and 2 watchdogs
  • 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
    
  • 2 × 16-bit advanced timers
    
  • 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)
    
  • 5 × 16-bit low-power timers
    
  • Secure RTC with sub-second accuracy and hardware calendar
    
  • 4 Cortex^®-A7 system timers (secure, non­secure, virtual, hypervisor)
    
  • 2 × independent watchdogs
    
• Hardware acceleration
  • ECDSA verification with SCA
    
  • HASH (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3), HMAC
    
  • 1 x true random number generator (6 triple oscillators)
    
  • 1 x CRC calculation unit
    
• Debug mode
  • Arm^® CoreSight™ trace and debug: SWD and JTAG interfaces usable as GPIOs
    
  • 4-Kbyte embedded trace buffer
    
• 3072-bit fuses including 96-bit unique ID, up to 1280 bits available for user
• All packages are ECOPACK2 compliant