CDC857-3DGGG4 [Texas Instruments]

These devices use a PLL to precisely align the feedback output to the clock input in frequency and phase. They distribute one differential clock input to ten differential outputs with low skew and jitter, adjusting duty cycles to 50% independent of input. Outputs can be enabled/disabled via a single G input. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer), while the CDC857-2 operates at 2.5 V for both. On-chip loop filter eliminates external RC networks. Requires stabilization time after power-up or signal changes.